1. Technical Field
The present invention relates to an improved method and system for data processing in general and, in particular, to an improved method and system for processing data related to an integrated circuit design. Still more particularly, the present invention relates to a method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms according to design stages.
2. Description of the Prior Art
A microelectronic integrated-circuit (IC) comprises a large number of electronic components that are fabricated by layering several different materials on a silicon wafer. The process of converting an electrical circuit specification into a geometric description known as layout is called physical design. Physical design is an extremely tedious and error-prone process because of the tight tolerance requirements and the minuteness of the individual electronic components. The layout is then checked to ensure that the IC design it represents meets all of the design requirements. The result is a set of design files with data stored under a particular format that describes the layout.
The design files are subsequently converted into pattern generator files that are utilized to produce patterns known as masks via an optical or electron beam pattern generator. During fabrication, these masks are utilized to pattern a silicon wafer under a sequence of photolithographic steps.
Due to the large number of electronic components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most stages of a physical design utilize Computer-Aided Design (CAD) tools extensively, and many stages have already been partially or fully automated. These stages include Partitioning, Floor Planning, Placement, and Routing.
Partitioningxe2x80x94A chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available. Therefore, it is normally partitioned by grouping the electronic components into blocks such as sub-circuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks, and number of interconnections between the blocks.
In large circuits, the partitioning process is often hierarchical, although non-hierarchical processes can also be utilized. The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is referred to as a netlist.
Floor Planning and Placementxe2x80x94Floor Planning is concerned with selecting good layout alternatives for each block of the entire chip, as well as between blocks and at the edges. Floor Planning is a critical step as it sets up the ground work for a good layout.
During Placement, the blocks are positioned exactly on the chip. The goal of placement is to find a minimum-area arrangement for the blocks that allows completion of inter-connections between the blocks. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated, and iterative improvements are made until the layout has minimum area and conforms to design specifications.
Routingxe2x80x94The objective of routing is to complete is the interconnections between blocks according to the specified netlist. First, the space not occupied by blocks, which is called the routing space, is partitioned into rectangular regions called channels and switch boxes. The goal of a router is to complete all circuit connections by utilizing the shortest possible wire length and the channel and switch boxes only.
Routing is usually done in two phases referred to as the global-routing and detailed-routing phases. In global routing, connections are completed between the proper blocks of the circuit, disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be utilized as a passageway for that wire. In other words, global routing specifies the loose route of a wire through different regions of the routing space.
Global routing is followed by detailed routing which completes point-to-point connections between terminals on the blocks. Loose routing is converted into exact routing by specifying the geometric information such as width of wires and their layer assignments. Detailed routing includes channel routing and switch box routing.
During a design process, checking tools are a key part of the design tool set, as they allow for IC designers to verify their work. These checking tools have many different functions, such as capacitance calculation and resistance-capacitance (RC delay) estimation. However, it has always been a problem for these checking tools to provide support throughout all the different development stages mentioned above. This is because in the early stages of a design, not much is known about the layout. Only as the design progresses, more is known about rough layout, and finally, there is wiring data available.
Nevertheless, IC designers need to perform timing analysis in early design stage to ensure that the target clock speed will be obtained. Hence, timing analysis has to be performed as early as possible in the design process. Because design data is available in different forms at the early stage of the design process, each according to a specific stage of the design process, therefore it has been a problem in the past for the IC designer to perform circuit analysis in the beginning or at the middle of the design process. Not only is the design in different data formats at different stages, but the various sections of a design may be at different levels, also. For example, a functional unit, such as random-logic macros, may be designed and wired, but no global wiring may have been completed; or even within one network, part of the circuit may be wired while another part may not be.
Consequently, it would be desirable to provide a method to perform circuit analysis on an integrated-circuit design having design data available in different forms according to design stages, even within one network.
In view of the foregoing, it is one object of the present invention to provide an improved method and system for data processing.
It is another object of the present invention to provide an improved method and system for processing data related to an integrated circuit design.
It is yet another object of the present invention to provide an improved method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms according to design stages.
In accordance with the method and system of the present invention, the integrated-circuit design includes multiple networks, and the different forms of design data may appear within one of the networks. For all of the networks within the integrated-circuit design, different forms of design data are categorized into at least three databases. The first of the at least three databases may contain three-dimensional extraction information, the second of the data-bases may contain wiring information, and the third of the databases may contain pre-wiring information. For each of the networks, a determination is made as to whether or not three-dimensional extraction information is available. In response to a determination that three-dimensional extraction information is available, performing circuit analysis by utilizing the three-dimensional extraction information.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.